设计了用于CMOS图像传感器内置流水线ADC的采样/保持电路,该电路具有10位采样精度和50 MHz采样速率,采用开关电容电荷重分布式结构,加入图像传感器的黑光校准功能。放大器采用全差分套筒式共源共栅增益增强型结构,保证了所需的增益和带宽。电路采用0.18μmCMOS工艺实现。HSPICE仿真结果表明,电路可在5 ns内达到0.05%的精度;对于24.0218 MHz、±0.5 V摆幅的正弦输入信号,SNDR和SFDR分别达到62.47 dB和63.73 dB,满足系统要求。 A sample / hold circuit for a CMOS pipeline image sensor with built-in pipelined ADC is designed. The circuit has 10-bit sampling rate and 50 MHz sampling rate. It adopts the switched-capacitor charge redistribution structure and incorporates the black-light calibration function of the image sensor. The amplifier features a fully differential sleeve cascode gain enhancement architecture that ensures the desired gain and bandwidth. Circuit using 0.18μmCMOS technology. HSPICE simulation results show that the circuit can achieve 0.05% accuracy in 5 ns. The SNDR and SFDR of ± 0.5 V swing sinusoidal input signal at 24.0218 MHz achieve 62.47 dB and 63.73 dB, respectively, which meets the system requirements.