As the feature size of integrated circuits is reduced to the deep sub-micron level or the nanometer level, the interconnect delay is becoming more and more important in determining the total delay of a circuit. Re-synthesis after floorptan is expected to be very helpful for reducing the interconnect delay of a circuit. In this paper,a force-balance-based re-synthesis algorithm for interconnect delay o ptimization after floorplan is proposed. The algorithm optimizes the inter connect delay by changing the operation scheduling and the functional unit allocation andbinding. With this method the number and positions of all functional units are not changed, but some operations are allocated or bound to different units. Preliminary experimental results show that the interconnect wire delays are reduced efficiently without destroying the floorplan performance.