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This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory,in which the cell device and chip circuit are developed and optimized.In order to solve the speed problem of giga-level NOR flash in the deep submicron process,the models of long bit-line and word-line are first given,by which the capacitive and resistive loads could be estimated.Based on that,the read path and key modules are optimized to enhance the chip access property and reliability.With the measurement results,the flash memory cell presents good endurance and retention properties,and the macro is operated with 1-ls/byte program speed and less than 50-ns read time under 3.3 V supply.
This paper presents a 65-nm 1-Gb NOR-type floating-gate flash memory in which the cell device and chip circuits are developed and optimized. Order to solve the speed problem of giga-level NOR flash in the deep submicron process , the models of long bit-line and word-line are first given, by which the capacitive and resistive loads could be estimated. Based on that, the read path and key modules are optimized to enhance the chip access property and reliability. Whith the measurement results, the flash memory cell presents good endurance and retention properties, and the macro is operated with 1-ls / byte program speed and less than 50-ns read time under 3.3 V supply.