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A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12×10 Gb/s high-density ultra-high speed parallel optical communication system.With critical limitations on power consumption,area and fabrication cost,the preamplifier achieves high performance,e.g.high bandwidth,high trans-impedance gain,low noise and high stability.A novel feed-forward common gate(FCG) stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom consuming approach to isolate a large input capacitance and using complex pole peaking techniques to substitute inductors to achieve bandwidth extension.A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature(PVT) variation.Two representative samples provide a trans-impedance gain of 53.9 dBΩ,a 3-dB bandwidth of 6.8 GHz,a power dissipation of 6.26 mW without power-configuration and a trans-impedance gain of 52.1 dBΩ,a 3-dB bandwidth of 8.1 GHz,a power dissipation of 6.35 mW with power-configuration,respectively.The measured average input-referred noise-current spectral density is no more than 28 pA/Hz~(1/2).The chip area is only 0.08×0.08 mm~2.
A power-configurable high performance preamplifier was implemented in standard 180-nm CMOS technology for 12 × 10 Gb / s high-density ultra-high speed parallel optical communication system. Most critical limitations on power consumption, area and fabrication cost, the preamp amplifier achieves high performance, eghigh bandwidth, high trans-impedance gain, low noise and high stability. A novel feed-forward common gate (FCG) stage is adopted to alleviate contradictions on trans-impedance gain and bandwidth by using a low headroom consuming approach to isolate a large input capacitance and using complex pole peaking technique to substitute inductors to achieve bandwidth extension. A multi-supply power-configurable scheme was employed to avoid wasteful power caused by a pessimistic estimation of process-voltage-temperature (PVT) variation. Two representative samples provide a trans-impedance gain of 53.9 dBΩ, a 3-dB bandwidth of 6.8 GHz, a power dissipation of 6.26 mW without power-configuration and a tra The ns-impedance gain of 52.1 dBΩ, a 3-dB bandwidth of 8.1 GHz, a power dissipation of 6.35 mW with power-configuration, respectively. The measured average input-referred noise-current spectral density is no more than 28 pA / Hz ~ (1/2). The chip area is only 0.08 × 0.08 mm ~ 2.