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本文描述了第一代和第二代通用逻辑门(ULG)的集成线路。ULG 是由两个相同的电流导引线路组成的单级结构,用这些 ULG 实现四个输入变量〈或少一些〉的全部逻辑函数所需要的延迟时间,是同具有相同制造工艺的单级 EDL 电流开关射极跟随器(CSEF)门的延迟时间很接近。通过比较用于实现四输入函数的硅区面积可以看出:ULG 的基本功耗和功率延迟乘积则优于 CSEF。ULG 是为了用最少的门级来实现逻辑结构而研制的。在另一篇介绍了有关一个设计例子的文章中,指出了这种门级的减少,以及这种 ULG 在实现逻辑结构时,性能有很大的改进,这是由于采用了 ULG 后,能非常有效地分解和组合逻辑函数,这是个优点。
This article describes the integrated circuit for first generation and second generation general purpose logic gates (ULGs). The ULG is a single-stage structure consisting of two identical current-steering circuits. The delay time required to implement all of the logic functions of the four input variables with these ULGs is the same as the single-stage EDL with the same manufacturing process The current switch emitter follower (CSEF) gate delay time is very close. By comparing the silicon area used to implement the four-input function, it can be seen that ULG’s basic power and power delay products outperform CSEF. The ULG was developed to implement the logical structure with the minimum gate level. In another article introducing a design example, this reduction in gate level was pointed out and the performance of the ULG in implementing the logical structure has been greatly improved due to the very good It is an advantage to effectively decompose and combine logic functions.