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本文描述的频率合成器是应低功耗便携式无线电台(电池供电)之需要而研制的。其设计方法与当前国内外无线电台中广泛使用的数字式频率合成器有所不同,它即使工作在甚高频或更高的频率范围,也只需要低速数字电路就能满足。因此可以采用 CMOS 逻辑电路,使功耗降低到500毫瓦以下。功耗的降低是依据下述原理:将压控振荡器的输出(f_(vco))先同一参考频率混频,取其差频,使其降到 CMOS逻辑电路的速度范围,然后加入锁相环路,通过程序控制实现频平合成。为××型选址通信双工移动无线电台设计的这种低功耗频率合成器已经做出样机,工作频率在甚高频段,频率间隔为25kHz,50kHz,100kHz。样机采用国产CMOS 逻辑电路构成。本文将以频率覆盖:下频段:51～59MHz,上频段:81～89MHz。频段间隔为25kHz 的低功耗合成器为例,叙述其工作原理,介绍实际线路。最后,对付波问题作了较为详细的分析,并从环路上推导出其运算公式。
The frequency synthesizer described in this article was developed to meet the needs of low-power portable radios (battery-powered). Its design method is different from the digital frequency synthesizer widely used in radio stations at home and abroad. It can only meet low-speed digital circuits even in the frequency range of VHF or higher. Therefore, CMOS logic can be used to reduce power consumption to less than 500 milliwatts. Power consumption is reduced according to the following principles: the voltage-controlled oscillator output (f vco) first mixed with the same reference frequency, take the difference frequency to make it down to the CMOS logic speed range, and then add the phase-locked Loop, through the program control to achieve frequency synthesis. This low-power frequency synthesizer designed for × ×-type site-addressed duplex mobile radio has been prototyped with very high frequency operating frequencies of 25kHz, 50kHz and 100kHz. Mock-up using domestic CMOS logic circuit. This article will cover the frequency: the next band: 51 ~ 59MHz, the band: 81 ~ 89MHz. An example of a low-power synthesizer with 25 kHz band spacing is to describe its working principle and introduce the actual line. Finally, the issue of dealing with waves is analyzed in more detail, and the formulas for its operation are deduced from the loop.