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针对数字化稳控设备的测试需求,设计了基于ARM+FPGA架构的数字化测试仪。在测试仪中,使用FPGA完成报文编码、光以太网应用、SFP模块驱动等功能。在计算SMV报文的一次码值时,根据FPGA的特点使用了适合硬件计算的Cordic算法,很好地完成了多路SMV报文输出的功能。测试仪在工程中稳定应用,满足了数字化稳控设备的测试需求。
Aiming at the requirement of testing digital control equipment, a digital tester based on ARM + FPGA is designed. In the tester, using FPGA to complete message encoding, optical Ethernet applications, SFP module driver and other functions. According to the characteristics of FPGA, a Cordic algorithm suitable for hardware calculation is used in calculating one code value of the SMV message, and the function of outputting the multiple SMV messages is completed well. Tester in the stable application of the project to meet the test requirements of digital stability control equipment.