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硅通孔中的缺陷不仅会导致硅通孔网络中传输延迟变化,也会引起对故障更为敏感的跳变延迟波动.本文基于时间数字转换原理提出一种非侵入式、皮秒级精度的绑定前硅通孔测试方法来检测电阻开路故障和泄漏故障.把硅通孔看作是驱动门的容性负载,遍历环状缩减单元的脉冲将会一直被缩减,直到该脉冲消失.将脉冲的缩减量数字化成一个数字码并与预期无故障信号的数字码进行比较.使用HSPICE在45 nm CMOS集成电路工艺库下模拟故障检测实验.实验结果表明本文方案能够检测到0.2 k?以上的电阻开路故障和等效泄漏电阻40 M?以下的泄漏故障.与现有方案相比,本文方案测试精度可以达到皮秒级,具有更大的故障检测范围以及质量分级能力,对初始输入信号频率或测试时钟信号频率无严格限制,可测试性设计面积开销相比于晶片面积可以忽略不计.
The defects in through-silicon vias not only lead to the variation of transmission delay in through-silicon vias, but also to the transition delay transitions that are more sensitive to faults.In this paper, a non-intrusive, picosecond-precision Binding pre-silicon through-hole test to detect open-circuit and open-drain faults The through-silicon via is considered as a capacitive load that drives the gate and the pulse traversing the ring-shaped reduction cell will be reduced until it disappears. The amount of pulse reduction is digitized into a digital code and compared with the digital code expected to be fault-free. HSPICE is used to simulate fault detection experiments at a 45 nm CMOS integrated circuit. The experimental results show that the proposed scheme can detect over 0.2 kΩ Resistance open circuit fault and equivalent leakage resistance of leakage fault below 40 M. Compared with the existing scheme, the scheme of this paper can achieve picosecond accuracy, with greater fault detection range and quality grading capability, the initial input signal frequency Or test clock signal frequency is not strictly limited, testable design area overhead compared to the wafer area can be neglected.