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提出了一种适用于高速、单级低分辨率流水线结构ADC的全差分动态比较器.由于采用了电流源耦合和差分对输入结构,比较器的翻转阈值电压可以设计为任意值.与传统的比较器相比,该比较器较好地兼顾了面积、功耗以及速度等方面,在这些方面有了较大的改进.该比较器在0.35μmCMOS工艺下完成流片,面积为30μm×70μm.仿真和测试结果表明,该比较器可以在2Vpp的输入信号和1GHz的时钟频率下工作,在3.3V的电源电压下,功耗仅为181μW.速度/功耗比达到了5524GS/J.
A fully differential dynamic comparator suitable for high speed, single-stage, low-resolution pipeline ADCs is proposed. The flip-flop threshold voltage of the comparator can be designed to any value due to the current source coupling and the differential pair input structure. Compared with the comparator, the comparator has better performance in these aspects, such as area, power consumption and speed, etc. The comparator achieves a chip area of 30μm × 70μm under a 0.35μm CMOS process. The simulation and test results show that the comparator can operate at a 2Vpp input signal and a clock frequency of 1GHz, consuming only 181μW at a supply voltage of 3.3V, achieving a speed / power ratio of 5524GS / J.