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本文提出的设计方案,以极低的附加硬件资源覆盖了包括附加电路在内的所有单重固定故障、交叉点故障、邻线桥接故障和几乎所有的多重故障。同现今通行的设计方案相比,具有下列明显优点:1) 极低的附加硬件资源;2) 极高的故障被测度;3) 对可编程逻辑阵列的正常操作没有影响;4) 减少了测试延迟;5) 故障检测异常简单。
The design presented in this paper covers all single-fixed failures, cross-point faults, adjacent-bridge faults and almost all multi-faults including additional circuits with very little additional hardware resources. Compared with the current design, it has the following obvious advantages: 1) very low additional hardware resources; 2) very high fault is measured; 3) has no effect on the normal operation of the programmable logic array; 4) reduces the test Delay; 5) fault detection is very simple.