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众所周知,目前集成电路的功耗正变得越来越高。电路功耗密度的增长速度十分惊人,使得功耗管理几乎对每一类设计都变成了一个日益严峻的问题。从ASIC设计的角度来看,面向SoC的高效功耗管理技术从架构设计阶段就成为IC设计的一部分,而低功耗实现的技术则需要应用于从RTL到GDSⅡ设计的每一阶段。本文将着重介绍基于通用功耗格式(CPF:Common Power Format)的完整低功耗设计流程。
As we all know, the current power consumption of integrated circuits is getting higher and higher. The rate of increase of circuit power density is staggering, making power management an increasingly serious problem for almost every type of design. From the point of view of ASIC design, the efficient power management technology for SoCs has become part of IC design from the architecture design stage, and the technology of low power implementation needs to be applied to every stage from RTL to GDS II design. This article will focus on a complete low-power design flow based on the Common Power Format (CPF).