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提出了一款低功耗、大动态范围输入的sigma-delta(∑-Δ)调制器设计。调制器采用前馈结构与一比特量化器,前馈结构降低了系统对积分器内运算放大器线性度以及转换速率的需求。积分内的运算放大器采用两级运放来满足大摆幅输出和高线性度性能要求。通过蒙特卡洛仿真分析验证,该两级运放在不同工艺角下具有良好的增益线性度性能。∑-Δ调制器整体电路在0.18μm CMOS工艺下实现,面积为0.23 mm2。后仿结果显示,在采用1.8 V电源电压供电,5 kHz,1.4 V峰-峰值正弦波输入信号,14 kHz信号带宽,过采样倍数为512的条件下,该调制器可以达到87 dB信噪失真比,整体电路消耗的电流为530μA。
A sigma-delta (Σ-Δ) modulator design with low power consumption and large dynamic range input is proposed. The modulator uses a feedforward structure and a bit quantizer. The feedforward structure reduces the system’s need for linearity and slew rate of the op amp within the integrator. The op-amp op-amp uses two stages of op amps to meet the large-swing output and high-linearity performance requirements. Through Monte Carlo simulation analysis and verification, the two-stage op amp has good gain linearity performance under different process angles. The Σ-Δ modulator overall circuit is implemented in a 0.18μm CMOS process with an area of 0.23 mm2. The post-mortem results show that the modulator achieves 87 dB of signal-to-noise distortion using a 1.8 V supply voltage, a 5 kHz, 1.4 V peak-to-peak sine wave input signal, a 14 kHz signal bandwidth, and an oversampling factor of 512 The current consumed by the overall circuit is 530μA.