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采用FPGA(field programmable gate array)设计基于原模图低密度奇偶校验(low density parity check,LDPC)码的联合信源信道译码器,信道部分和信源部分都是由原模图LDPC码组成。在原模图LDPC码联合译码器的硬件实现架构中,通过2步循环扩展得到了适合硬件实现的准循环原模图LDPC码,译码器信息的迭代更新采用TDMP(Turbo decoding message passing)分层译码算法,采用的归一化最小和算法使得P-JSCD(photograph-based joint source and channel decoding)具有部分并行结构。最后,为了降低资源消耗和译码延迟,采用了提前终止迭代策略。基于FPGA平台的硬件实现结果表明,该联合译码器的译码性能非常接近相应的浮点算法,并且最大时钟频率达到193.834 MHz,吞吐量为24.44 Mbit/s.
The FPGA (field programmable gate array) is used to design a joint source channel decoder based on the LDPC code. The channel part and the source part are composed of the original model LDPC code composition. In the hardware implementation of the original model LDPC code decoder, a quasi-cyclic LDPC code suitable for hardware implementation is obtained by 2-step cyclic expansion. The iterative update of the decoder information is implemented by using a TDMP (Turbo decoding message passing) Layer decoding algorithm, using the normalization minimum and the algorithm makes P-JSCD (photograph-based joint source and channel decoding) has a partial parallel structure. Finally, in order to reduce the resource consumption and decoding delay, an early termination iteration strategy is adopted. The hardware implementation based on FPGA platform shows that the performance of the joint decoder is very close to that of the corresponding floating-point arithmetic, and the maximum clock frequency reaches 193.834 MHz and the throughput is 24.44 Mbit / s.