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A novel frequency compensation technique for three-stage amplifier with dual complex pole-zero (DCP) cancellation is proposed. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that frequency response of the three-stage amplifier exhibits that of a single-pole system. Thus the gain-bandwidth (GBW) is expected to be increased several times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a big load capacitor. A GBW 4.63 MHz, DC gain 100 dB, PM 90o and power dissipation 0.87 mW can be achieved for a load capacitor 100 pF with a single Miller compensation capacitor 2 pF at a ±1V supply in a standard 0.6-μm CMOS technology.
A novel frequency compensation technique for three-stage amplifier with dual complex pole-zero (DCP) cancellation is proposed. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that frequency response of the three-stage amplifier exhibits that of a single-pole system. Thus, the gain-bandwidth (GBW) is expected to be increased several times compared to the conventional nested miller compensation (NMC) approach. A big load capacitor. A GBW 4.63 MHz, DC gain 100 dB, PM 90 o and power dissipation 0.87 mW can be achieved for a load capacitor 100 pF with a single Miller compensation capacitor 2 pF at a ± 1 V supply in a standard 0.6-μm CMOS technology.