目前使用的数字逻辑电路有与组装互连延迟相当的延迟时间。在高速情况下,电路的互连不再是简单的短路,而呈现传输线特性。与传输线相关的现象,即由反射和串扰引起的额外的电压和电流,称之为互连噪音。在近来的文献中,对于反射和用于控制反射的传输线端接提供了充分的资料。然而,由于缺乏有关文献,串扰仍是数字系统设计者感到有些神秘的问题,致使系统设计过于谨慎,甚至更坏,使系统不能工作。尽管广泛地用ECL 和肖特基TTL 设计中型计算机,但是大型主机电路仍然趋向于选择 Digital logic circuits currently in use have a latency equivalent to that of assembly interconnects. At high speeds, the interconnection of the circuits is no longer a simple short circuit, but presents the transmission line characteristics. The phenomena associated with the transmission line, the extra voltage and current caused by reflection and crosstalk, are called interconnection noise. In recent literature, sufficient information has been provided for the reflection and termination of transmission lines used to control reflections. However, due to a lack of literature, crosstalk remains a mystery for digital system designers, rendering system design too cautious or even worse for the system to work. Despite the widespread design of midsize computers with ECLs and Schottky TTLs, mainframe circuitry still tends to choose