The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment.It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT.The dV/dt rate,gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike.The device with a higher dV/dt rate,gate-collector capacitance,gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on.By optimizing these parameters,the dV/dt induced voltage spike can be effectively controlled. The effect of dV / dt on the IGBT gate circuit in IPM is analyzed both experiment and experiment. It shows a voltage slope applied across the collector-emitter terminals of the IGBT. parasitic capacitances of the IGBT. dV / dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. device with a higher dV / dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV / dt induced self turn-on.By optimizing these parameters, the dV / dt induced voltage spike can be effectively controlled.