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提出了一种可供CMOS锁相环使用的自由调整的自校准技术。与传统的自校准技术相比,新的自校准方案不需要使用参考电压源,而且自校准过程内嵌在锁相环的锁定过程中,所以新的自校准方案减少了芯片的面积:与自校准有关电路的面积只有0.0068 mm2。所设计的PLL采用0.13μm CMOS工艺,工作频率范围在25～700MHz之间。测试表明,当压控振荡器工作在700 MHz的时候,其8倍降频之后的87.5 MHz输出信号的相位噪音在1MHz频率偏移处为-131dBc/Hz。
A free self-calibration technique for CMOS phase-locked loop is proposed. Compared with the traditional self-calibration technology, the new self-calibration scheme does not need to use the reference voltage source, and the self-calibration process is embedded in the locking process of the phase-locked loop, so the new self-calibration scheme reduces the chip area: The circuit area for calibration is only 0.0068 mm2. The design of the PLL using 0.13μm CMOS technology, operating frequency range between 25 ~ 700MHz. Tests show that the phase noise of an 87.5 MHz output signal after 8 times its down-regulation is -131 dBc / Hz at a 1 MHz frequency offset when the VCO is operating at 700 MHz.