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本文设计了基于FPGA的吞吐率达到100Mbit/s可配置MIMO检测器,可以根据信道估计模块提供的信道状态信息,实现MMSE和QRM-MLD(基于QR分解和M算法的最大似然检测)两种MIMO检测算法间的切换。本设计基于4发4收的MIMO场景,将MMSE的求逆运算与QRM-MLD的QR分解部分共用硬件资源,在Xilinx的FPGA上实现的结果表明,本设计与两个独立的检测器相比,大大节省了FPGA的乘法器资源和逻辑资源。
This paper designs a FPGA-based MIMO detector with a throughput of 100Mbit / s. The MMSE and QRM-MLD (maximum likelihood detection based on QR decomposition and M algorithm) can be implemented according to the channel state information provided by the channel estimation module Switching between MIMO detection algorithms. The design is based on 4 4 receiving MIMO scenarios, hardware resources will be shared between the MMSE inverse operation and the QR decomposition part of QRM-MLD. The result of Xilinx FPGA implementation shows that this design compares with two independent detectors , Greatly saving FPGA multiplier resources and logic resources.