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设计了应用于3G无线通信中频接收机的10位100 MSPS双通道交织流水线A/D转换器,采用0.18μm CMOS工艺流片。电路工作电压为3.3 V,核心部分功耗不超过70mW。为了减小A/D转换器的功耗,采用两路并行交织结构,并在两个通道间进行运放共享。运放采用套筒式结构,以进一步节省功耗。对于交织结构,如何保证线性度是设计的关键。线性度主要受直流失调失配、增益失配及采样时间失配的限制。分别采用共享运放、提高每个通道的精度,以及全局被动采样(Global Passive Sampling),减小这些失配的影响。除通道间失配外,还分析了传统双采样电路中的输出开关电荷注入以及断开开关电容串扰对线性度的影响。为了保证A/D转换器的线性度,通过修改时序,消除了以上开关的非理想因素。后仿真结果表明,在100 MSPS采样率下,输入信号带宽为47.6 MHz;最差工艺角(ss,120℃)下,杂散无失真动态范围(SFDR)大于70 dB,信杂比(SNDR)大于60 dB。
A 10-bit, 100 MSPS dual interleaved pipelined A / D converter designed for use in 3G wireless IF receivers is designed using a 0.18μm CMOS process chip. Circuit operating voltage of 3.3 V, the core part of the power consumption does not exceed 70mW. In order to reduce the power consumption of the A / D converter, two parallel interleaving structures are adopted and the op amp is shared between the two channels. Op amp using sleeve structure, to further save power. For the interleaved structure, how to ensure the linearity is the key to design. Linearity is mainly limited by DC offset mismatch, gain mismatch and sampling time mismatch. The use of shared op amps, respectively, to improve the accuracy of each channel, as well as global passive sampling (Global Passive Sampling), reduce the impact of these mismatches. In addition to the mismatch between channels, the effects of the injection of the output switch charge and the crosstalk of the switched capacitor on the linearity of the conventional double sampling circuit are analyzed. In order to ensure the linearity of the A / D converter, by modifying the timing, the non-ideal factors of the above switch are eliminated. The simulation results show that the input signal bandwidth is 47.6 MHz at the sampling rate of 100 MSPS and the spurious distortion free dynamic range (SFDR) is greater than 70 dB at the worst-case process corner (ss, 120 ℃) Greater than 60 dB.