论文部分内容阅读
This paper proposes a novel noise optimization technique.The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier(LNA)circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation,respectively,by mathematical analysis and reasonable approximation methods.LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae.We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process.The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW,demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.
This paper proposes a novel noise optimization technique. The technique gives an analytical formula for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively , by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formula. We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process. the measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.