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单载波超宽带通信系统的均衡在芯片实现中面临高吞吐率、高性能和低复杂度3方面问题。该文从广播结构电路表达、delayed-sign-LMS系数更新算法和寄存器重采样芯片设计方法学3个角度提出一种适合芯片实现的判决反馈均衡(DFE)结构。该结构以标准LMS-DFE为基础,克服自适应反馈滤波器中迭代界对吞吐率的影响,解决广播结构中输入高扇出带来的延时和功耗问题。仿真结果表明:与直接结构LMS-DFE相比,该结构性能损失在0.1dB之内。芯片综合表明,基于Smic.18 CMOS工艺,吞吐率达到125Mb/s,与广播结构delayed-LMS-DFE相比,面积减少23%,功耗降低33%。
The equalization of single-carrier ultra-wideband communication system faces the problems of high throughput, high performance and low complexity in the chip implementation. This paper presents a decision feedback equalization (DFE) architecture suitable for chip implementation from three perspectives: broadcast structure circuit representation, delayed-sign-LMS coefficient update algorithm, and register resampling chip design methodology. Based on the standard LMS-DFE, this architecture overcomes the influence of iterative boundaries in the adaptive feedback filter on the throughput and solves the delay and power consumption problems caused by the high fanout in the broadcast structure. The simulation results show that the performance loss of this structure is within 0.1dB compared with the direct structure LMS-DFE. Chip synthesis shows that based on the Smic.18 CMOS process throughput rate of 125Mb / s, compared with the broadcast structure delayed-LMS-DFE, 23% reduction in area, power consumption decreased by 33%.