The product of the cutoff frequency and breakdown voltage( fT×BVCEO) is an important figure of merit(FOM) to characterize overall performance of heterojunction bipolar transistor(HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator(SOI) Si Ge HBT to simultaneously improve the FOM of fT×BVCEOand thermal stability is presented by using two-dimensional(2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness(TBOX) on fT, BVCEO, and the FOM of fT×BVCEOare presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEOto some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT,BVCEO, and the FOM of fT×BVCEOcan be improved by increasing SOI insulator Si O_2 layer thickness TBOXin SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of Si O_2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEOis improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer into collector region provides an effective method to improve SOI Si Ge HBT overall performance. The product of the cutoff frequency and breakdown voltage (fT × BVCEO) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N + -buried layer into Firstly, in order to show some (2D) numerical simulation through SILVACO device simulator. The introduction of SOI structure remarkably reduces the electron concentration in collector region near the SOI substrate insulation layer (TBOX) on fT, BVCEO, and the FOM of fT × BVCEOare presented. , obviously reduces fT, slightly increases BVCEOto some extent, but only eventually degrades the FOM of fT × BVCEO. Although the fT, BVCEO, and the FOM of fT × BVCEOcan be improved by increasing SOI insulat or Si O_2 layer thickness TBOXin SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of Si O_2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the forth problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N + -buried layer is introduced only into collector region to not only improve the FOM of fT × BVCEO, but also weaken the self-heating effect of the device. Thus, the effect of the location of the thin N + -buried layer in collector region is investigated in detail. the FOM of fT × BVCEOis improved and the device temperature decreases as the N + -buried layer shifts toward the SOI substrate insulation layer. The approach to introducing a thin N + -buried layer into coll ector region provides an effective method to improve SOI Si Ge HBT overall performance.