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利用一款型号为EP2C5T的FPGA中和S52单片机实现完成了逻辑分析仪系统的采样、触发,存储、控制、接口等核心硬件模块;通过Verilog HDL硬件描述语言与原理图设计相结合的混合输入方式,完成了系统核心功能模块的仿真及实测,采样频率可达100MHz,有16个采用通道,并用单片机实现了阈值设置及彩色液晶显示。
The core hardware module of sampling, triggering, storing, controlling and interface of the logic analyzer system is realized by using an FPGA of type EP2C5T and the S52 microcontroller. The hybrid input mode combining Verilog HDL hardware description language and schematic design , Completed the simulation and measurement of the system’s core functional modules, the sampling frequency up to 100MHz, 16 channels, and the use of SCM threshold settings and color LCD display.