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A high-performance low-powerΣΔanalog-to-digital converter(ADC) for digital audio applications is described.It consists of a 2-1 cascadedΣΔmodulator and a decimation filter.Various design optimizations are implemented in the system design,circuit implementation and layout design,including a high-overload-level coefficient-optimized modulator architecture,a power-efficient class A/AB operational transconductance amplifier,as well as a multi-stage decimation filter conserving area and power consumption.The ADC is implemented in the SMIC 0.18-μm CMOS mixed-signal process.The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm~2,which dissipates only 2.1 mA quiescent current in the analog circuits.
A high-performance low-power ΣΔ analog-to-digital converter (ADC) for digital audio applications is described. It consists of a 2-1 cascaded ΣΔ modulator and a decimation filter. Popular design optimizations are implemented in the system design, circuit implementation and layout design , including a high-overload-level coefficient-optimized modulator architecture, a power-efficient class A / AB operational transconductance amplifier, as well as a multi-stage decimation filter conserving area and power consumption. The ADC is implemented in the SMIC 0.18- μm CMOS mixed-signal process. The experimental chip achieves a peak signal-to-noise-plus-distortion ratio of 90 dB and a dynamic range of 94 dB over 22.05-kHz audio band and occupies 2.1 mm ~ 2, which dissipates only 2.1 mA quiescent current in the analog circuits.