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采用1.6μm CMOS工艺的10位、5M取样/秒、两步闪烁模拟/数字转换器(ADC)要求54k mil~2的有效面积和350mW的功耗。全微分结构是以电阻器串和电容器阵列结构为基础的。一个采样/保持电路(S/H)置于此结构内部。这个结构是用增加分辨率来消除变得更加严格的定时参数。使用最小的元件匹配和比较器失调对消能够保证单调性。闪烁转换器内面积和功率随不断增加的分辨率的指数增长使10位分辨率难以实现。为了减少面积和降低功耗,分级结构采用2~(n/2)-1个比较器,而不用2~n-1个比较器。早期的两步结构受运算放大器增益和建立时间的限制。这个新的结构则省去了运效,从而消除了可能的误差源。高速ADC设计的关键是比较器。采用简单的数级比较器模型,能够确定获得最快响应的比较器最佳级数。比较器增益级用一个二极管连接的MOS晶体管负载,因而无需共模反馈(CMFB)。CMFB会增加转换器的复杂度并占用面积、增加功耗。
10-Bit, 5M Sample / s Using 1.6μm CMOS Process, Two-Step Flashing Analog-to-Digital Converter (ADC) Requires 54k mil ~ 2 Active Area and 350mW Power Dissipation. Fully differential structure is based on the resistor string and capacitor array structure. A sample / hold circuit (S / H) is placed inside this structure. This structure is to increase the resolution to eliminate the more stringent timing parameters. Monotonicity can be guaranteed with minimum component matching and comparator offset cancellation. The 10-bit resolution is difficult to achieve with the exponential increase of area and power in the flash converter with increasing resolution. In order to reduce the area and reduce power consumption, the hierarchical structure uses 2 ~ (n / 2) -1 comparators instead of 2 ~ n-1 comparators. The early two-stage structure was limited by the op amp gain and settling time. This new structure eliminates the need for performance, eliminating possible sources of error. The key to high-speed ADC design is the comparator. Using a simple digital comparator model, the best series of comparators for the fastest response can be determined. The comparator gain stage is loaded with a diode-connected MOS transistor, eliminating the need for common-mode feedback (CMFB). CMFB increases converter complexity and footprint, increasing power consumption.