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主要介绍在逻辑资源少的现场可编程门阵列(FPGA)上实现高级数据加密标准(AES)算法设计。首先描述了AES加密算法,并在FPGA上优化实现AES算法,设计结构采用多轮加密共用一个轮运算的顺序结构,加密和解密模块共用密钥扩展模块,减少资源占用,在低时钟频率下保持较高的性能。采用了16位的并行总线通信接口,利用先进先出缓冲器(FIFO)对输入输出数据进行缓存。最后通过仿真和实测表明,在50MHz时钟下加解密速率可达530Mb/s。
Mainly introduces the Advanced Data Encryption Standard (AES) algorithm design on field programmable gate array (FPGA) with less logic resources. Firstly, the AES encryption algorithm is described and the AES algorithm is optimized on the FPGA. The design structure uses a round robin sequence with a round of operations. The encryption and decryption module shares the key expansion module to reduce the resource occupation and keep it at a low clock frequency High performance. Using a 16-bit parallel bus communication interface, using first-in first-out (FIFO) buffers input and output data. Finally, through the simulation and measurement show that the encryption and decryption rate up to 530Mb / s at 50MHz clock.