MOS晶体管MOS晶体管的结构如下图所示,它的两个邻近电级区域之间的导电性可由区域间隙上面的绝缘栅极上所加的电压来控制。由于控制电压是加到绝缘的电极上,所以输入阻抗非常高。如图所示,称为源和漏的两个P型区,以极小的间距(典型值为5μm)扩散到N型衬底 The structure of the MOS transistor MOS transistor is shown in the following figure. The conductivity between two adjacent potential regions of the MOS transistor can be controlled by the voltage applied to the insulation gate above the interstitial region. Since the control voltage is applied to the insulated electrode, the input impedance is very high. As shown, two P-type regions, called sources and drains, diffuse to N-type substrate with very small pitch (typically 5 μm)