电子工程师正面临著新一代集成电路带来的在设计流程中增加循环时间的新的挑战。这种集成电路的开关时间延时以亚纳秒来计算,平均系统时钟速度超过100MHz。作为互联综合(IS)的发明者,明导资讯公司的Interconnectix业务部创造了新一代基于革新技术的解决方案。IS将时序和信号完整性分析规则与平 Electronic engineers are facing the new challenges of increasing the cycle time in the design flow with the new generation of integrated circuits. The switching time delay of this integrated circuit is calculated in sub-nanoseconds, with an average system clock speed of over 100 MHz. As Interconnect Integrated (IS) inventor, Mentor Graphics Interconnectix business unit creates a new generation of innovative technology-based solutions. IS combines timing and signal integrity rules with flatness