论文部分内容阅读
在本文中，我们提出了一种离散小波变换（DWT）及其逆变换（IDWT）的VLSI结构，这一结构利用DWT／IDWT的结构和数值特性大大降低了系统的实现规模，同时由于采用了并行流水线和平衡数据通道等技术，可以获得每个时钟两个数据的处理速度和五个时钟节拍的流水线时延．基于硬件描述语言VHDL的模拟和综合结果表明，采用1．5μmCMOS工艺时，电路的规模为5058单元面积，在最坏情况下，最高时钟频率约可达55MHz，数据处理速度达到110Mpoints／s．
In this paper, we propose a VLSI structure of discrete wavelet transform (DWT) and its inverse transform (IDWT), which uses the structure and numerical characteristics of DWT / IDWT to greatly reduce the system’s implementation scale. At the same time, Parallel pipeline and balanced data channel technology, you can get two data per clock processing speed and five clock tick pipeline delay. The simulation and synthesis results based on the hardware description language VHDL show that when the 1.5μm CMOS process is used, the scale of the circuit is 5058 unit area. In the worst case, the highest clock frequency can reach about 55MHz and the data processing speed reaches 110Mpoints / s.