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提出一种适于实现数据通路的FPGA逻辑模块。每个模块包括4个基于全加器的逻辑单元。逻辑单元分为组合和时序两部分：组合部分以1位全加器为基础，有两个输出端，这两个输出端在必要时可以合并在一起以实现功能更复杂的单输出函数；时序部分基于可配置的D型触发器。逻辑单元在结构上保证了电路的高速性。工艺映射的实验结果显示，在实现数据通路中的常用电路时，新逻辑单元比基于LUT的FPGA单元平均大约节省75%的MOS管数。
An FPGA logic module suitable for realizing data path is proposed. Each module includes four full adder-based logic cells. The logic unit is divided into two parts, combining and timing: the combining part is based on a 1-bit full adder and has two outputs that can be combined together as necessary to achieve a more complex single-output function; the timing Partly based on configurable D-type flip-flops. Logic unit in the structure to ensure that the circuit speed. Experimental results from process mapping show that the new logic cells save on average about 75% fewer MOS transistors than LUT-based FPGA cells when implementing commonly used circuits in the data path.