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介绍了一种单片集成的3.125 Gb/s接收器的设计,它适用于IEEE 802.3ae四通道10 Gb/s以太网接口.电路采用了多相时钟结构和并行采样技术以降低电路速度要求.电荷泵采用了常跨导偏置技术以降低环路对工艺、电源电压和温度变化的敏感度.时钟数据恢复电路采用1/5速率时钟降低振荡器的设计难度,时钟恢复的同时完成1:5解串功能,降低了电路功耗.电路采用0.18μm CMOS工艺设计和仿真,总体功耗为95 mW,625 MHz恢复时钟的输出抖动小于75 ps,电路在3.125 Gb/s的数据率和各种工艺角下工作正确.
A monolithic integrated 3.125 Gb / s receiver design is introduced for a four-channel IEEE 802.3ae 10 Gb / s Ethernet interface using a multi-phase clock architecture and parallel sampling techniques to reduce circuit speed requirements. The charge pump uses a conventional transconductance bias technique to reduce the sensitivity of the loop to process, supply voltage and temperature variations. The clock data recovery circuit uses a 1/5 rate clock to reduce the design difficulty of the oscillator, while the clock recovery completes 1: 5 deserialization reduces circuit power consumption The circuit is designed and simulated in 0.18μm CMOS technology with an overall power consumption of 95 mW and a 625 MHz recovery clock with an output jitter of less than 75 ps at 3.125 Gb / Work under the correct kind of technology.