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本文介绍了高速双极LSI中的一种新的超自对准工艺技术(SST)。分为SST-1和SST-2两种类型。前者用一次光刻形成完整的微细晶体管有源区域和P~+多晶硅基极,用其制作的器件速度高且功耗低,后者的优点是,把多晶硅N~+发射极以及P~+基极两电极通过发射极图形的腐蚀进行隔离,隔离宽度达亚微米。采用此工艺后,浅结性能稳定,电路速度高而且易于实现大规模集成。SST-1用于NTL电路后,获得了传输延迟时间63ps/门、功耗延迟乘积是43fJ/门的超高速性能。用SST-2试制的1K位RAM和8×8位并行乘法器,其参数是存取时间2.7ns,功耗500mW,运算时间10ns,功耗660mW高速工作。可以确认该工艺对提高电路性能是有效的。下面将对SST晶体管的结构、工艺、IC样品的特性以及在LSI中的应用结果逐一加以论述。
This article describes a new super-self-aligned technology (SST) in high-speed bipolar LSIs. Divided into SST-1 and SST-2 two types. The former uses a lithography to form a complete active region of fine transistors and a base of P ~ + polysilicon. The device fabricated by the method has the advantages of high speed and low power consumption. The latter has the advantage that the polysilicon N + emitter and the P + The base two electrodes are isolated by the erosion of the emitter pattern, with isolation widths up to submicron. After adopting this craft, the shallow knot performance is steady, the circuit speed is high and easy to realize the large-scale integration. SST-1 is used NTL circuit, get the transmission delay time of 63ps / door, power delay product is 43fJ / door ultra-high speed performance. The 1K bit RAM and 8 × 8 bit parallel multiplier produced by SST-2 have the parameters of 2.7ns access time, 500mW power consumption, 10ns operation time and 660mW power consumption. It can be confirmed that the process is effective for improving the circuit performance. The following will be SST transistor structure, process, IC sample characteristics and application results in the LSI one by one to be discussed.