针对低频下数字集成电路实现时序收敛需要插入大量缓冲器而导致芯片布线困难、运行时间较长等问题,提出了一种降低时钟树级数与增加保持时间余量相结合的时钟树综合方案。基于CSMC 0.35μm CMOS工艺,采用提出的方案,使用IC Compiler和Prime Time工具,分别完成了应用于高精度隔离型Σ-ΔADC芯片的低速数字滤波器的物理设计以及静态时序分析。结果表明,与传统方案相比,保持时间负松弛总值降低了95.62%,时序收敛所需缓冲器个数减少了约98.13%,运行时间缩短了97.25%,有效地降低了布线拥塞程度,快速有效地实现了时序收敛。 Aiming at the problem of timing convergence in low frequency digital integrated circuits, a large number of buffers need to be inserted, which leads to the difficulties in the routing of the chips and the long running time. A clock tree synthesis scheme is proposed to reduce the number of clock trees and increase the holding time margin. Based on the CSMC 0.35μm CMOS technology, the proposed scheme was used to design the low-speed digital filter for high-precision isolated Σ-Δ ADC chips and to analyze the static timing using IC Compiler and Prime Time tools respectively. The results show that the total negative relaxation time of holding time is reduced by 95.62% compared with the traditional scheme, the number of buffers required for timing closure is reduced by about 98.13% and the operating time is shortened by 97.25%, which effectively reduces the degree of wiring congestion, Effectively achieve the timing closure.