Semiconductor technology continues advancing,while global on-chip interconnects do not scale with the same pace as transistors,which has become the major bottleneck for performance and integration of future giga-scale ICs.Threedimensional(3D) integration has been proposed to sustain Moore’s law by incorporating through-silicon vias(TSVs) to integrate different circuit modules in the vertical direction,which is believed to be one of the most promising techniques to tackle the interconnect scaling problem.Due to its unique characteristics,there are many research opportunities,and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-onChips(SoCs).Firstly,we use existing 2D SoCs algorithms to minimize test time for individual embedded cores.In addition,vertical interconnects,i.e.,TSVs that are used to construct the test wrapper should be taken into consideration as well.This is because TSVs typically employ bonding pads to tackle the misalignment problem,and they will occupy significant planar chip area,which may result in routing congestion.In this paper,we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively.It is composed of two steps,i.e.,scan chain allocation and functional input/output insertion,both of which can reduce TSV count significantly.Through extensive experimental evaluations,it is shown that the test wrapper chain structure designed by our method can reduce the number of test TSVs dramatically,i.e.,as much as 60.5% reductions in comparison with the random method and 26% in comparison with the intuitive method. Semiconductor technology continues advancing, while global on-chip interconnects do not scale with the same pace as transistors, which has become the major bottleneck for performance and integration of future giga-scale ICs.Threedimensional (3D) integration has been proposed to sustain Moore’s law by incorporating through-silicon vias (TSVs) to integrate different circuit modules in the vertical characteristics, which is believed to be one of the most promising techniques to tackle the interconnect scaling problem. Due to its unique characteristics, there are many research opportunities, and in this paper we focus on the test wrapper optimization for the individual circuit-partitioned embedded cores within 3D System-onChips (SoCs). Firstly, we use existing 2D SoCs algorithms to minimize test time for individual embedded cores. Additionally, the vertical interconnects, ie, TSVs that are used to construct the test wrapper should be taken into consideration as well. This is because TSVs typically employ bonding p ads to tackle the misalignment problem, and they will occupy significant planar chip area, which may result in routing congestion. In this paper, we propose a series of heuristic algorithms to reduce the number of TSVs used in test wrapper chain construction without affecting test time negatively.It is composed of two steps, ie, scan chain allocation and functional input / output insertion, both of which can reduce TSV count significantly.Through extensive experimental evaluations, it is shown that the test wrapper chain structure designed by our method can reduce the number of test TSVs dramatically, ie, as much as 60.5% reductions in comparison with the random method and 26% in comparison with the intuitive method.