以TI公司的最新型多核DSP TMS320C6678为研究对象,提出一种基于四个多核DSP的雷达对抗侦查仿真机核心模块的硬件设计方法与实现,重点详细介绍了所设计的处理器及其时序要求、时钟电路、复位电路、SRIO交换电路的设计实现方法。该设计能够很好地满足现今日益发展的雷达对抗侦察算法对于信号处理硬件的高性能需求,具有很高的实用价值。 Taking TI’s latest multi-core DSP TMS320C6678 as the research object, a hardware design method and implementation of the radar countermeasure detection simulation core module based on four multi-core DSPs are put forward. The emphasis is put on the design of the processor and its timing requirements, Clock circuit, reset circuit, SRIO switching circuit design and implementation. The design can well meet the current development of radar reconnaissance algorithms for high-performance signal processing hardware needs, has a high practical value.