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SET不需要精确的光刻工艺和金属化技术就可以获得良好的性能。在SET结构中使用砷掺杂多晶硅作为发射极电极部分。这种电极被作成倒置梯形。利用两层多晶硅之间腐蚀速度的不同来形成这种倒置梯形结构。离子注入后用化学腐蚀方法开出基板接触窗口。发射极扩散层和基极接触之间的间距为0.4微米或更小。 |S_(21)~(ei)|的截止频率约为8.4千兆赫,比相同发射极尺寸的通常的平面晶体管的截止频率高2千兆赫。集成的SET的上升时间为150微微秒。
SET does not require precise lithography and metallization techniques to achieve good performance. Arsenic-doped polysilicon is used as the emitter electrode portion in the SET structure. This electrode is made upside down trapezoid. This inverted trapezoidal structure is formed using the difference in etching rate between two layers of polycrystalline silicon. After ion implantation chemical etching method out of the substrate contact window. The spacing between the emitter diffusion layer and the base contact is 0.4 microns or less. The cut-off frequency of S_ (21) ~ (ei) | is about 8.4 gigahertz, which is 2 GHz higher than the cut-off frequency of a typical planar transistor of the same emitter size. Integrated SET rise time of 150 picoseconds.