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采用标准0.18μm CMOS工艺,设计了一种连续速率时钟与数据恢复(CDR)电路。该CDR电路主要由半速率鉴频鉴相器、多频带环形压控振荡器、电荷泵和判决电路等模块组成。其中,半速率鉴频鉴相器主要由四个双边沿触发器组成,结构简单,功耗和面积相应降低。多频带环形压控振荡器同时满足了较宽的调谐范围和较低的调谐增益,可以解决高振荡频率和低调谐增益之间的矛盾。电荷泵采用增益自举共源共栅放大器和互补开关电路结构,减小了各种非理想因素的影响。并行判决电路实现数据的1∶2分接输出。仿真结果表明,该CDR电路能正常恢复622~3 125 Mbit/s的伪随机数据。版图尺寸为691μm×543μm。在1.8 V电源电压下,输入伪随机速率3 125 Mbit/s时,功耗为120 mW,恢复出的数据和时钟的抖动峰峰值分别为5.18和4.41 ps。
Using a standard 0.18μm CMOS process, a continuous rate clock and data recovery (CDR) circuit is designed. The CDR circuit is mainly composed of a half-rate frequency-phase detector, a multi-band ring voltage-controlled oscillator, a charge pump and a decision circuit. Among them, the half-rate phase frequency detector is mainly composed of four double-edge flip-flop, simple structure, the corresponding reduction in power consumption and area. Multi-band ring voltage controlled oscillator to meet both the wide tuning range and lower tuning gain, you can solve the high oscillation frequency and low tuning gain between the contradictions. Charge pump bootstrap cascode amplifier and complementary switching circuit structure, reducing the impact of various non-ideal factors. Parallel decision circuit to achieve data 1: 2 tap output. Simulation results show that the CDR circuit can recover 622 ~ 3 125 Mbit / s pseudo-random data normally. The layout size is 691μm × 543μm. Power consumption is 120 mW with a pseudo-random rate of 3 125 Mbit / s at a 1.8 V supply voltage, with jitter peaks of 5.18 and 4.41 ps for the recovered data and clock, respectively.