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本文介绍一种采用双层n沟道多晶硅栅工艺的全译码(与TTL相容)电改写8K位MOS ROM。存储单元由叠栅结构的单管组成,其浮动栅只盖住沟道的一部分,并扩展到沟道外的源扩散区的清除复盖层上。通过热电子从短沟道(3.5μm)注入到浮动栅来编码,典型的为100ms/字。通过电子从浮动栅的Fowler-Nordheim 发射完成成组清除。在清除期间,为了避免雪崩击穿电流过大,在清除复盖层加了40nm～50nm 的氧化层并采用了斜坡电压。存储器在读、编码和清除操作中用标准电压(±5V,+12V),编码用一个高压单脉冲(+26V),斜坡清除电压最大值为+35V。典型的读出时间为250ns。从存储实验数据外推法(Extrapolation of storage data)(在125℃,400小时)可以予示,90%以上的存储电荷可望保持100年以上。每个存储单元允许写入次数在10000次以上。面积为19.7mm~2的芯片装在24引线双列直插式封装中。
This article presents a fully transcoded (TTL compatible) electrically rewritten 8K bit MOS ROM using a double n-channel polysilicon gate process. The memory cell consists of a single-stacked gate stack of which the floating gate covers only a portion of the trench and extends to the clear cap of the source diffusion region outside the trench. Encoded by hot electrons injected into the floating gate from a short channel (3.5 μm), typically 100 ms / word. Group clearing is done electronically by Fowler-Nordheim emission from the floating gate. During the blanking period, in order to prevent the avalanche breakdown current from being too large, an oxide layer of 40nm ~ 50nm was added to the clear cap layer and a ramp voltage was applied. The memory uses a standard voltage (± 5V, + 12V) for reading, encoding and clearing operations, a high voltage single pulse (+ 26V) for coding, and a ramp clear voltage of + 35V maximum. The typical readout time is 250ns. From the Extrapolation of storage data (at 125 ° C for 400 hours) it can be shown that more than 90% of the stored charge is expected to remain above 100 years. Each memory cell allows writing more than 10,000 times. An area of 19.7mm ~ 2 chip mounted in a 24-lead dual in-line package.