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ＳＤＨ系统的ＳＴＭ—Ｎ线路的误码监视码定义为２４Ｎ比特的ＢＩＰ（ＢｉｔＩｎｔｅｒＬｅａｖｅｄＰａｒｉｔｙ）。实现ＢＩＰ算法的硬件规模随着传送速率的提高而成比例的增多。例如，适用于ＳＴＭ—１６（２．４８８３２Ｇｂｉｔ／ｓ）的ＢＩＰ码其长度为３８４比特，很明显线路误码监视的硬件占ＳＤＨ处理硬件的很大比例。为解决此问题，本论文提出一种新的误码监视方法。该方法在发送端适用于ＩＴＵ—Ｔ建议的误码监视码；但在接收端，需将收到的ＢＩＰ全部信息减少后进行线路误码监视。若采用这种监视方法，既适用国际标准接口，又能减少硬件规模而不降低性能。例如，ＳＴＭ—１６减少３０００门的硬件（占ＳＤＨ接收处理部分的２０％）。
The error monitoring code of the STM-N line of the SDH system is defined as 24N bits of BitInterLeavedParity. The scale of the hardware implementing the BIP algorithm increases proportionately with the transfer rate. For example, the BIP code for STM-16 (2.48832 Gbit / s) is 384 bits long and it is clear that the hardware for line error monitoring accounts for a large percentage of the SDH processing hardware. To solve this problem, this paper presents a new error monitoring method. This method is suitable for the error monitoring code recommended by the ITU-T at the transmitting end. However, at the receiving end, all the received information of the BIP needs to be reduced to monitor the line error. If using this monitoring method, both international standard interface, but also reduce the hardware size without reducing performance. For example, the STM-16 reduces hardware by 3000 (accounting for 20% of the SDH receive processing portion).