Synopsys公司推出的一种独特的工具ECO Compiler,能将工程更改指令自动综合进已经完全综合并进行了布局布线的设计中。从而在IC设计周期的末端可能节省几个星期的重复工作。 Synopsys ECO Compiler与实际上已是业界标准的综合产品Synopsys DesignCompiler共用,以改善结果的质量和设计效率。这样,新工具大大增加了ASIC开发中的自动化程 ECO Compiler, a unique tool from Synopsys, automatically integrates engineering change instructions into a fully integrated and place-and-route design. This can save weeks of repetitive work at the end of the IC design cycle. Synopsys ECO Compiler is shared with Synopsys DesignCompiler, an industry standard synthesis product, to improve the quality and design efficiency of results. In this way, new tools have greatly increased the automation of ASIC development