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以前已经介绍过一种4096×1双极型动态RAM。这里将介绍一种采用同样单层布线(I~3L)工艺、管腿兼容的16384×1动态RAM。这种16K存储单元由两支NPN、PNP晶体管组成。存储保持在NPN晶体管的集-基电容上,该晶体管产生β倍的电荷读出。由外围读出-驱动电路确定的单元尺寸是0.7 mil~2,用单层布线的存储器芯片尺寸为26000 mil~2。地址译码是借助于如图1所示的快速、低功耗树译码结构实现的。从两个地址引线来的输入信号被预先译码,在四个缓冲输出中得到一个高电平信号。然
A 4096 × 1 bipolar dynamic RAM has been introduced previously. Here will introduce a same single-layer wiring (I ~ 3L) process, leg-compatible 16384 × 1 dynamic RAM. This 16K memory cell consists of two NPN, PNP transistors. The memory is held on the collector-base capacitance of the NPN transistor, which produces β times the charge readout. By the peripheral readout - drive circuit to determine the size of the unit is 0.7 mil ~ 2, with single-layer wiring of the memory chip size of 26000 mil ~ 2. Address decoding is achieved by means of a fast, low-power tree decoding structure as shown in FIG. Input signals from the two address pins are pre-decoded, resulting in a high signal on the four buffered outputs. Of course