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基于0.18μm CMOS工艺,设计了一种双信道并行时钟数据恢复(CDR)电路,它由1个锁相环(PLL)型CDR和1个相位选择/相位插值(PS/PI)型CDR结合实现。与传统的并行CDR相比,该CDR电路不需要本地参考时钟。PLL型CDR中环形压控振荡器的延迟单元采用电感峰化技术,拓展了带宽,实现了较高的振荡频率;电荷泵采用自举基准和运放,改善了充放电电流匹配。PS/PI型CDR中Bang-Bang型鉴相器结构简单,具有较好的鉴相功能;PS/PI电路比传统结构少2个相位选择器。仿真结果表明,当输入并行数据速率为5Gb/s时,恢复出的2组时钟与数据的峰峰抖动值分别为6.1ps,8.1ps和8.7ps,11.2ps。电路核心模块的功耗为172.4mW,整体电路版图面积为(1.7×1.585)mm~2。
Based on a 0.18μm CMOS process, a dual-channel parallel clocked data recovery (CDR) circuit is designed, which consists of a phase-locked loop (PLL) type CDR and a phase selection / phase interpolation (PS / PI) . The CDR circuit does not require a local reference clock compared to traditional parallel CDRs. PLL-type CDR in the annular voltage-controlled oscillator delay unit inductors peaking technology to expand the bandwidth and achieve a higher oscillation frequency; charge pump bootstrap reference and operational amplifier to improve the charge and discharge current matching. The PS-PI type of CDR Bang-Bang type phase detector has a simple structure and good phase discrimination function. The PS / PI circuit has two phase selectors less than the conventional structure. The simulation results show that the peak-to-peak jitter values of the two clocks and the data recovered are 6.1ps, 8.1ps and 8.7ps, 11.2ps respectively when the input parallel data rate is 5Gb / s. The power consumption of the circuit core module is 172.4mW, the overall circuit layout area is (1.7 × 1.585) mm ~ 2.