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信息产业飞速发展,芯片设计的复杂性与日俱增。在复杂的电路设计中,经常包含某些功能未知的模块,这样的电路称为部分实现电路。为了保证产品设计的正确性,对部分实现电路进行等价性验证,提出了一种基于可满足性的优化算法。首先对部分实现组合电路进行“逻辑锥”分割;其次根据匹配的逻辑锥创建Miter电路,并且使用符号模拟技术对电路中的功能未知模块进行变量约束;最后对多个Miter电路的合取范式依次进行可满足性验证。通过在包含单个未知模块的ISCAS’85基准电路以及包含若干大小相近未知模块的组合电路上得到的实验数据,表明了此算法能够较好地提高电路检错率。
The rapid development of the information industry, the complexity of chip design increasing. In complex circuit design, often contains some unknown function modules, such circuits are called partial implementation of the circuit. In order to ensure the correctness of the product design and verify the equivalence of some of the circuits, an optimization algorithm based on satisfiability is proposed. First of all part of the realization of combinational circuit “Logical Cone ” segmentation; followed by matching logic cone to create Miter circuit, and the use of symbolic simulation technology to function unknown module in the circuit variable constraints; Finally, the combination of multiple Miter circuit The paradigm sequentially verifies satisfiability. The experimental data obtained from the ISCAS’85 reference circuit including a single unknown module and the combined circuit including several unknown modules shows that this algorithm can improve the circuit error detection rate better.