论文部分内容阅读
现参见图例,图1表示基本的取样保持鉴相器电路的波形。鉴相器产生的斜坡电压用锯齿波10表示,在参考脉冲即 R 脉冲出现的每一时刻,锯齿波到达零。在 R 脉冲之间,斜坡电压线性上升到最大值。当控制脉冲即 C 脉冲出现时,斜坡电压被取样和保持,(如虚线13所示),从而产生鉴相器输出。C 脉冲由压控振荡器驱动的分频器一类发生器来产生,C 脉冲频率是与鉴相器的输出成正比例的。如果 C 脉冲频率低于 R 脉冲频率,如图1所示,
Referring now to the drawings, FIG. 1 shows waveforms of a basic sample-and-hold phase detector circuit. The ramp voltage generated by the phase detector is represented by sawtooth wave 10, which reaches zero at each moment when the reference pulse, or R pulse, appears. Between R pulses, the ramp voltage rises linearly to its maximum value. When the control pulse, the C pulse, appears, the ramp voltage is sampled and held (as shown by the dotted line 13), resulting in the phase detector output. The C pulse is generated by a voltage-controlled oscillator-driven divider-type generator whose C-pulse frequency is proportional to the output of the phase detector. If the C pulse frequency is lower than the R pulse frequency, as shown in Figure 1,