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实现了64位串行和4096位串一并一串型结构的CCD器件。以三氯乙烯(TCE)氧化1100埃加Si_3N_3300埃的夹层结构做存贮栅,以湿氧氧化加Si_3N_4的夹层为转移栅制造了P沟铝-硅交迭栅结构CCD。这种结构有效地克服了典型P沟硅栅工艺中的滞后现象、栅漏电与表面反型现象。存贮与转移栅开启电压分别为0.5～1V和5～6V。势阱存贮时间达数秒,它的长短和深浅标志CCD研制的品质因素。SiO_2-Si界面态俘获是转移效率的主要影响因素,准静态C-V测试以及转移效率测试表明,获得了界面态密度<1×10~(10)Cm~(-2)ev~(-1)。64位CCD转移效率在fe为100KC时达99.99％。4096位CCD在fe为1MC时达99.99％,64位芯片尺寸0.9×3.6mm~3。4096位芯片尺寸为3.6×3.9mm~2。
A 64-bit serial and 4096-bit serial and serial structure CCD devices are realized. A p-channel Al-Si overlapped gate CCD was fabricated by sandwiching the sandwich structure with 1100 CEEGE Si_3N_3300 angstroms by TCE and using the wet oxide and Si_3N_4 interlayer as the transfer gate. This structure effectively overcomes the hysteresis phenomenon in the typical P-type silicon gate process, gate leakage and surface inversion phenomenon. Storage and transfer gate open voltage were 0.5 ~ 1V and 5 ~ 6V. Potential storage time of a few seconds, its length and depth of flag CCD developed quality factors. The SiO_2-Si interfacial state capture is the main influencing factor of the transfer efficiency. Quasi-static C-V test and transfer efficiency test show that the interface state density is less than 1 × 10 ~ (10) Cm ~ (-2) ev ~ (-1). The 64-bit CCD transfer efficiency is 99.99% at fe of 100KC. The 4096 CCD reaches 99.99% when the fe is 1MC, and the size of the 64-bit chip is 0.9 × 3.6mm ~ 3.4096 and the chip size is 3.6 × 3.9mm ~ 2.