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针对专用集成电路(ASIC)设计中功能验证的效率和完备性问题,以验证方法学手册(VMM)为基础搭建了串行高级技术附件(SATA)控制器分层式验证平台.验证组件的实现大量重用验证知识产权核(VIP),在采用随机激励的基础上以覆盖率统计驱动验证的过程,根据SATA控制器的功能设计记分牌进行结果的自动化比对.实验结果表明,这些方法提高了功能验证的效率,保证了验证的完备性,最终功能覆盖率达到98.25%.
To address the issue of efficiency and completeness of functional verification in ASIC design, a Serial Advanced Technology Attachment (SATA) controller hierarchical verification platform is built on the Validation Methodology Manual (VMM) A lot of reuses verify the intellectual property nucleus (VIP), based on the random stimulus based on the coverage of the statistics-driven verification process, according to the SATA controller function design scoreboard automatic comparison of the results.The experimental results show that these methods improve The efficiency of functional verification, to ensure the integrity of the verification, the final functional coverage of 98.25%.